1. Field of the Invention
The present invention is related to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device, such as a high voltage IC equipped with a high voltage element and a low voltage element, and a method of manufacturing the same.
2. Description of the Related Art
The progress of a high voltage IC (HVIC) has been remarkable over these years. In a high voltage IC, a single chip seats low voltage elements, such as a control circuit and various types of protection circuits, and high voltage elements. For instance, high voltage elements include those elements utilizing a resurf technique such as a horizontal MOS transistor while low voltage elements include CMOS transistors, bipolar transistors, and the like.
FIG. 8 is a cross sectional view of a conventional semiconductor device (a high voltage IC), generally denoted at 500, which includes a high voltage element region 510 and a low voltage element region 520 and which is an example that a horizontal n-ch MOS FET is used as a high voltage element and a CMOS transistor is used as a low voltage element. The semiconductor device 500 includes a p− semiconductor substrate 1 of silicon. An n+ buried diffusion layer 2 and n− epitaxial layer 3 are formed on the semiconductor substrate 1. A p− diffusion region 4, an n+ diffusion region 5 and a p+ diffusion region 6 are formed in the epitaxial layer 3, and a polysilicon electrode 7 and an aluminum electrode 8 are disposed on the epitaxial layer 3. Further, silicon oxide films 9a and 9b are formed on the epitaxial layer 3 by using a LOCOS method. The film thickness of the silicon oxide film 9b formed in the low voltage element region 520 is sufficiently thinner than that of the silicon oxide film 9a formed in the high voltage element region 510 (JP 64-77941, A).